Comparative Study of Surface and Buried Channel 0.25 μm pMOSFETs

This paper presents a comparison between two designs of 0.25 μm gate length pMOSFETs processed with either a surface channel (SC) P+ polysilicon gate or a buried channel (BC) N+ polysilicon gate. Except for the channel and gate architectures, the other pMOSFET design parameters such as gate oxide (6 nm), source/drain engineering with LDD are similar. Criteria for this comparison are the threshold voltage (VT), the short channel effect (SCE) control, the off-state leakage current (Ioff) and the saturation drain current (Idsat). The more simplified gate engineering of PMOS device processed with N+ polysilicon gate suffers from a 12% drive capability decrease for a given Ioff.