Title :
CLAY: a malleable-cell multi-cell transistor matrix approach for CMOS LAYout synthesis
Author :
Kollaritsch, P. ; Lusky, S. ; Prasad, S. ; Potter, N.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
CLAY takes a netlist partitioned down to the transistor level, a technology file with an arbitrary number of metal layers, and constraints on aspect and I/O signal positions to produce mask geometries. CLAY attempts to capture, in software, layout knowledge at the transistor level (allowing variable-shaped cells including heights) and at the floorplan level for VLSI sized examples. CLAY compares well with standard cell and manual approaches.<>
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; masks; CLAY; CMOS layout synthesis; I/O signal positions; VLSI sized examples; aspect ratios; constraints; floorplan level; layout knowledge; malleable-cell multi-cell transistor matrix approach; mask geometries; metal layers; technology file; transistor level partitioned netlist; variable-shaped cells; CMOS technology; Circuits; Costs; Geometry; Instruments; Logic design; Signal design; Signal synthesis; Software libraries; Very large scale integration;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122481
