• DocumentCode
    1943215
  • Title

    Allocation of FIFO structures in RTL data paths

  • Author

    Khanna, Heman ; Balakrishnan, M.

  • Author_Institution
    Cadence Design Syst. (I) Pvt. Ltd., Noida, India
  • fYear
    1997
  • fDate
    4-7 Jan 1997
  • Firstpage
    130
  • Lastpage
    133
  • Abstract
    Along with the functional units, storage and interconnects also contribute significantly to the data path cost. This paper addresses the issue of reducing the storage and interconnect cost by allocating queues for storing variables. In contrast to the earlier works, we support “regular” cdfgs and multi-cycle functional units for queue synthesis. Initial results on HLS benchmark examples have been encouraging and show the potential of data path cost reduction using queue synthesis. A novel feature of our work is the formulation of the problem for a variety of FIFO structures with their own “queueing” criteria
  • Keywords
    high level synthesis; queueing theory; FIFO structure; HLS; RTL data path cost; cdfg; interconnect; multicycle functional unit; queue synthesis; storage; Automatic control; Clocks; Cost function; High level synthesis; Merging; Shift registers; Terminology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1997. Proceedings., Tenth International Conference on
  • Conference_Location
    Hyderabad
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-7755-4
  • Type

    conf

  • DOI
    10.1109/ICVD.1997.568064
  • Filename
    568064