Title :
A 7 ns cycle, high speed dual compare CAM in 0.6 /spl mu/m GaAs
Author :
Venkataraman, M. ; Pai, M. ; Canaga, S.
Author_Institution :
Vitesse Semicond. Corp., Camarillo, CA, USA
fDate :
Oct. 29 1995-Nov. 1 1995
Abstract :
A 256 entry by 14-bit dual compare content addressable memory (CAM) with a fast hit detect access time of 5.5 ns and a cycle time of 7 ns is described in this paper. In addition, the CAM flags multiple hits and outputs the hit address when a single hit has occurred. The size of the CAM is 3.5 mm/spl times/8 mm. The power dissipation, at a vtt of -2.0 V, and 85/spl deg/C is 8.8 W. The chip was fabricated using Vitesse´s 0.6 /spl mu/m H-GaAsIII enhancement/depletion MESFET technology.
Keywords :
III-V semiconductors; MESFET integrated circuits; content-addressable storage; field effect memory circuits; gallium arsenide; -2 V; 0.6 micron; 5.5 ns; 7 ns; 8.8 W; GaAs; H-GaAsIII enhancement/depletion MESFET technology; Vitesse; content addressable memory; high speed dual compare CAM; hit detect access time; CADCAM; Circuit faults; Circuit testing; Clocks; Computer aided manufacturing; Gallium arsenide; Read only memory; Signal generators; Table lookup; Throughput;
Conference_Titel :
Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1995. Technical Digest 1995., 17th Annual IEEE
Conference_Location :
San Diego, CA, USA
Print_ISBN :
0-7803-2966-X
DOI :
10.1109/GAAS.1995.529019
