Hardware implementation for census 3D disparity map with dynamic search range estimation

In this paper, a new hardware implementation for the real time disparity map is presented. The real time disparity map includes the Dynamic Search Range Estimation, Disparity estimation, and Error Correction. Our demonstrated design flow shows an approach to implementation and hardware architecture of real-time disparity map estimation. This design is efficiently synthesized on Xilinx vertex 5 VLX 330 FPGA. The resulting hardware implementation is analyzed and simulated for system clock speed 100MHz to verify adequate performance. Since the algorithm is not so complicated to adapt real-time hardware design, we successfully made system with FPGA Prototype design.