Title :
Well - Optimization for High Speed BICMOS Technologies
Author :
Klose, H. ; Meister, T. ; Hoffmann, B. ; Weng, J. ; PfÄffel, B.
Author_Institution :
Siemens AG, Corporate Research, Otto-Hahn-Ring 6, D-8000 Mÿnchen 83, F.R.G.
Abstract :
A high speed BICMOS process with a polysilicon bipolar transistor is presented. Using this technology the well optimization is outlined. Different approaches to construct the well are compared to Improve the high current behaviour of the bipolar transistor. Influences on the parasitics are discussed. Using the optimized process version bipolar transistors with a cut-off frequency of 9.5 GHz were fabricated.
Keywords :
BiCMOS integrated circuits; Bipolar transistors; CMOS process; Capacitance; Cutoff frequency; Degradation; Design optimization; Doping; Drives; Kirk field collapse effect;
Conference_Titel :
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location :
Montpellier, France
