Simulation of Layout-Dependent STI Stress and Its Impact on Circuit Performance

Author

Yang, Liu ; Li, Xiaojian ; Tian, Lilin ; Yu, Zhiping

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2009

fDate

9-11 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

The impact of STI stress with layout dependency on circuit performance is investigated. A 3D stress simulator has been developed using finite element method, which considers both the layout design and process information (PDK). The mobility change due to stress is included in the transistor modeling for circuit simulation. The circuit performance can thus be analyzed with nonlocal stress. As a test case, a buffered SR flip-flop was simulated with and without STI stress considered. It can be seen that STI stress has non-negligible influence on the circuit performance.

Keywords

CMOS integrated circuits; MOSFET; finite element analysis; flip-flops; integrated circuit layout; isolation technology; semiconductor device models; semiconductor process modelling; stress analysis; stress effects; 3D stress simulator; CMOS devices; buffered SR flip-flop; circuit performance; finite element method; layout design; layout-dependent STI stress simulation; mobility change; nonlocal stress; shallow trench isolation; transistor modeling; Circuit optimization; Circuit simulation; Computational modeling; Finite element methods; Flip-flops; MOSFETs; Performance analysis; Strontium; Thermal expansion; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on

Conference_Location

San Diego, CA

ISSN

1946-1569

Print_ISBN

978-1-4244-3974-8

Electronic_ISBN

1946-1569

Type

conf

DOI

10.1109/SISPAD.2009.5290196

Filename

5290196