Study on Influence of Device Structure Dimensions and Profiles on Charge Collection Current Causing SET Pulse Leading to Soft Errors in Logic Circuits

Current responses due to the strike of ionized particle onto nMOS transistor of 90 nm and 55 nm generation have been analyzed through 3D device simulations. From the current response, duration of charge collection (t_cc) is determined, which correlated strongly with the width of erroneous pulse (SET pulse). Causes of the difference between t_cc values of 90 nm and 55 nm generation MOSFETs have been investigated and it is found that the difference in STI depth and width of p-well contact line between these two generations influences t_cc mainly. This is because that the resistance below the p-well contact affects the ability to pull out the excess holes remaining in the channel region. It is also shown that there is room for reducing t_cc and hence SET pulse width by well profile engineering.