Low-power configurable processor array for DLMS adaptive filtering

In this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance and power dissipation. This architecture is then extended to derive a configurable processor array (CPA), which is configurable for filter order, sample period and power reduction factor. The hardware overhead incurred for configurability is minimal