Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D package

This paper presents micro fabrication process and wafer level integration of a silicon carrier, in which optimized liquid cooling layers are embedded. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. Wafer bonding are carried out with AuSn-solder which deposited by evaporation and the shear strength is higher than 27.2 MPa after bonding, which is high enough for application. The advantage of this 3-D stacking method is that it provides a method of simultaneous realizing electrical interconnection and fluidic path between two carriers and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.