Impact of packaging design on reliability of large die Cu/low-κ (BD) interconnect

Author

Chai, T.C. ; Zhang, Xiaowu ; Li, H.Y. ; Sekhar, VN ; Hnin, W.Y. ; Thew, M.L. ; Navas, OK ; Lau, John ; Murthy, R. ; Balakumar, S. ; Tan, Y.M. ; Cheng, C.K. ; Liew, SL ; Chi, D.Z. ; Zhu, W.H.

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore

fYear

2008

fDate

27-30 May 2008

Firstpage

38

Lastpage

45

Abstract

This paper presents the study on the effect of low k stacked layer, chip pad design structures, and shift pad design TM of a large die size Cu/low kappa (BDtrade) chip for improving assembly and reliability performance on organic buildup substrate FCBGA (FlipChip ball grid array). Bump shear characterization has been performed on the integrity of different stacked layer and pad structure, supported by bump shear modeling analysis. Initial reliability testing was performed on assembled package to identify the best choice of design and finally implemented on the reliability test vehicle for verification. In addition, a potential chip crack problem due to excessive warpage in FCBGA with large die assembly is examined and a simple failure criterion is proposed.

Keywords

ball grid arrays; circuit reliability; flip-chip devices; integrated circuit design; integrated circuit interconnections; integrated circuit testing; bump shear modeling analysis; chip pad design structures; flip chip ball grid array; packaging design; reliability testing; test vehicle; Assembly; Capacitive sensors; Circuit testing; Materials science and technology; Packaging; Passivation; Performance analysis; Performance evaluation; Protection; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 2008. ECTC 2008. 58th

Conference_Location

Lake Buena Vista, FL

ISSN

0569-5503

Print_ISBN

978-1-4244-2230-2

Electronic_ISBN

0569-5503

Type

conf

DOI

10.1109/ECTC.2008.4549948

Filename

4549948