Title :
A fast fault simulation algorithm for combinational circuits
Author :
Wuudiann Ke ; Seth, S. ; Bhattacharya, B.B.
Author_Institution :
Dept. of Comput. Sci., Nebraska Univ., Lincoln, NE, USA
Abstract :
The performance of a fast fault simulation algorithm for combinational circuits, such as the critical-path-tracing method, is determined primarily by the efficiency with which it can deduce the detectability of stem faults (stem analysis). A graph-based approach to perform stem analysis is proposed. A dynamic data structure, called the criticality constraint graph, is used during the backward pass to carry information related to self-masking and multiple-path sensitization of stem faults. The structure is updated in such a way that when stems are reached, their criticality can be found by looking at the criticality constraints on their fanout branches. Compared to the critical-path-tracing method, the algorithm is exact and does not require forward propagation of individual stem faults. Several examples which illustrate the power of the algorithm are given. Preliminary data on an implementation are also provided.<>
Keywords :
circuit analysis computing; combinatorial circuits; data structures; digital simulation; fault location; graph theory; backward pass; combinational circuits; critical-path-tracing method; criticality constraint graph; dynamic data structure; efficiency; fanout branches; fast fault simulation algorithm; graph-based approach; multiple-path sensitization; performance; self-masking; stem analysis; stem fault detectability; Analytical models; Circuit faults; Circuit simulation; Combinational circuits; Computational modeling; Computer simulation; Electrical fault detection; Fault detection; Logic circuits; Performance analysis;
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
DOI :
10.1109/ICCAD.1988.122486