DocumentCode
1944692
Title
Bit error rate performance evaluation of a Silicon-on-Insulator optical-network-on-chip router in a WDM configuration
Author
Parini, Alberto ; Bellanca, G. ; Annoni, Andrea ; Morichetti, Francesco ; Melloni, A. ; Strain, Michael J. ; Sorel, Marc ; Pareige, Christelle ; Gay, M. ; Bramerie, L. ; Thual, M.
Author_Institution
Lab. for Micro & Submicro Enabling Technol. of the Emilia-Romagna Region, Bologna, Italy
fYear
2013
fDate
22-26 Sept. 2013
Firstpage
1
Lastpage
3
Abstract
We present a microring-based integrated router in Silicon-on-Insulator technology suitable for optical networking at chip level. The switching functionalities in a 3-channels 10 Gbit/s WDM configuration are evaluated through the BER curves. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.
Keywords
error statistics; integrated optoelectronics; network-on-chip; silicon-on-insulator; telecommunication channels; telecommunication network routing; wavelength division multiplexing; 3-channel WDM configuration; BER curves; Si; bit error rate performance evaluation; bit rate 10 Gbit/s; microring-based integrated router; power penalty; silicon-on-insulator optical-network-on-chip router; switching functionalities;
fLanguage
English
Publisher
iet
Conference_Titel
Optical Communication (ECOC 2013), 39th European Conference and Exhibition on
Conference_Location
London
Electronic_ISBN
978-1-84919-759-5
Type
conf
DOI
10.1049/cp.2013.1572
Filename
6647765
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