DocumentCode
1944750
Title
Characterization of Field-Oxide-Transistor-Instabilities Caused by SOG-Planarization
Author
Vollmer, B. ; Roska, G. ; Winnerl, J.
Author_Institution
Siemens AG, Central Research and Development, Microelectronics, Otto-Hahn-Ring 6, D-8000 Mÿnchen 83, F.R.G.
fYear
1988
fDate
13-16 Sept. 1988
Abstract
A spin-on-glass planarization process in multilevel metallization can cause instabilities of metal-2-gate field oxid transistors. The threshold voltage shift of a p-channel transistor is reduced for negative gate bias and it can be accelerated by gate bias and temperature. The threshold voltage shift is caused by a thermally activated and field enhanced diffusion process. The planarization process leaves SOC inclusions, but the instabilities are also observed in strcutres where no inclusions are present.
Keywords
Bars; CMOS process; CMOS technology; Etching; Isolation technology; Metallization; Planarization; Stress; Temperature; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location
Montpellier, France
Print_ISBN
2868830994
Type
conf
Filename
5436915
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