DocumentCode :
1944901
Title :
Convex Channel Design for Improved Capacitorless DRAM Retention Time
Author :
Cho, Min Hee ; Shin, Changhwan ; Liu, Tsu-Jae King
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, Berkeley, CA, USA
fYear :
2009
fDate :
9-11 Sept. 2009
Firstpage :
1
Lastpage :
4
Abstract :
A convex channel surface with Si0.8Ge0.2 is proposed to enhance the retention time of a capacitorless DRAM generation 2 type of capacitorless DRAM cell. This structure provides a physical well together with an electrostatic barrier to more effectively store holes and thereby achieve larger sensing margin as well as retention time. The advantages of this new cell design as compared with the planar cell design are assessed via two-dimensional device simulations. The results indicate that the convex heterojunction channel design is very promising for future capacitorless DRAM.
Keywords :
DRAM chips; Ge-Si alloys; semiconductor device models; semiconductor materials; Si0.8Ge0.2; capacitorless DRAM cell; capacitorless DRAM generation 2 type; capacitorless DRAM retention time; cell design; convex channel design; convex channel surface; convex heterojunction channel design; electrostatic barrier; two-dimensional device simulation; Capacitors; Doping profiles; Electronic mail; Electrostatics; Germanium silicon alloys; Heterojunctions; Random access memory; Scalability; Silicon germanium; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on
Conference_Location :
San Diego, CA
ISSN :
1946-1569
Print_ISBN :
978-1-4244-3974-8
Electronic_ISBN :
1946-1569
Type :
conf
DOI :
10.1109/SISPAD.2009.5290254
Filename :
5290254
Link To Document :
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