DocumentCode :
1945003
Title :
Providing performance guarantees in multipass network processors
Author :
Keslassy, Isaac ; Kogan, Kirill ; Scalosub, Gabriel ; Segal, Michael
Author_Institution :
Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
fYear :
2011
fDate :
10-15 April 2011
Firstpage :
3191
Lastpage :
3199
Abstract :
Current network processors (NPs) increasingly deal with packets with heterogeneous processing times. As a consequence, packets that require many processing cycles can significantly delay low-latency traffic, because the common approach in today´s NPs is to employ run-to-completion processing. These difficulties have led to the emergence of the Multipass NP architecture, where after a processing cycle ends, all processed packets are recycled into the buffer and re-compete for processing resources. In this work we provide a model that captures many of the characteristics of this architecture, and consider several scheduling and buffer management algorithms that are specially designed to optimize the performance of multipass network processors. In particular, we provide analytical guarantees for the throughput performance of our algorithms. We further conduct a comprehensive simulation study that validates our results.
Keywords :
buffer storage; microprocessor chips; multiprocessing systems; buffer management algorithm; heterogeneous processing time; low-latency traffic; multipass network processors; performance guarantee; run-to-completion processing; Algorithm design and analysis; Delay; Process control; Program processors; Recycling; Scheduling; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
INFOCOM, 2011 Proceedings IEEE
Conference_Location :
Shanghai
ISSN :
0743-166X
Print_ISBN :
978-1-4244-9919-9
Type :
conf
DOI :
10.1109/INFCOM.2011.5935167
Filename :
5935167
Link To Document :
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