Title :
Reflowable ISM WLP
Author :
Jeung, Won Kyu ; Lim, Chang Hyun ; Yuan, Jingli ; Park, Seung Wook ; Choi, Seog Moon ; Yi, Sung
Author_Institution :
Samsung Electro-Mech. Co., Ltd., Suwon
Abstract :
A new ISM (image sensor module) WLP (wafer level package) for reflow process is designed, fabricated and tested. The proposed ISM WLP is composed of polymer bonding layer, glass cap wafer for particle free process and CIS (CMOS Image Sensor) chip wafer which has micro via hole interconnection. During the last decades, WLP is highlighted as the next generation ISM Package method for many advantages like high yield (particle free process), small form factor (3D interconnection), low assembly cost and so on. Nevertheless these benefits, there are some difficulties like micro via hole fabrication, low temperature insulation process (inside hole), bottom side oxide etching process, warpage control according to wafer level bonding using different material, and whole process temperature limitation for micro lens damage. Among various fabrication methods for ISM package, COB (Chip on board), COF (Chip on film), and L, T contact WLP from ShellCase are generally used. In case of COB and COF package, it has difficulty in particle control during assembly process. In case of ShellCase type WLP has very complicated fabrication process. Additionally, most of above package has disadvantage in size point of view. Through suggested ISM WLP using thru interconnection via is realized. And we can good photo image using fabricated WLP. It can not only solve problems of conventional packaging structures but also tremendously reduce the manufacturing & assembly cost (include time) of ISM package and realize real chip scale package.
Keywords :
CMOS image sensors; etching; microlenses; wafer bonding; wafer level packaging; 3D interconnection; CMOS image sensor chip wafer; Chip on film; ISM package method; ShellCase type WLP; bottom side oxide etching process; chip on board; glass cap wafer; image sensor module; low temperature insulation process; micro lens damage; micro via hole interconnection; particle free process; polymer bonding layer; reflow process; small form factor; wafer level bonding; wafer level package; warpage control; Assembly; Chip scale packaging; Costs; Fabrication; Image sensors; Process control; Process design; Testing; Wafer bonding; Wafer scale integration;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4549985