DocumentCode
1945057
Title
Technology Projection Using Simple Compact Models
Author
Wong, H. S Philip ; Wei, Lan ; Oh, Saeroonter ; Lin, Albert ; Deng, Jie ; Chong, Soogine ; Akarvardar, Kerem
Author_Institution
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
fYear
2009
fDate
9-11 Sept. 2009
Firstpage
1
Lastpage
8
Abstract
We review recent efforts to capture the device nonidealities for circuit-level technology projection for Si CMOS. We also give some examples of simple compact model development for assessing the circuit-level performance of exploratory devices such as III-V FET, carbon nanotube transistor, and nanoelectromechanical (NEM) transistors and relays.
Keywords
CMOS integrated circuits; integrated circuit modelling; silicon; CMOS circuit; Si; circuit-level performance; circuit-level technology; model development; parasitic capacitance; parasitic resistance; CMOS logic circuits; CMOS technology; Carbon nanotubes; FETs; III-V semiconductor materials; MOSFETs; Nanoscale devices; Parasitic capacitance; Semiconductor device modeling; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation of Semiconductor Processes and Devices, 2009. SISPAD '09. International Conference on
Conference_Location
San Diego, CA
ISSN
1946-1569
Print_ISBN
978-1-4244-3974-8
Electronic_ISBN
1946-1569
Type
conf
DOI
10.1109/SISPAD.2009.5290261
Filename
5290261
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