MFAST: a single chip highly parallel image processing architecture

Author

Pechanek, G.G. ; Stojancic, M. ; Vassiliadis, S. ; Glossner, C.J.

Author_Institution

Microelectron. Div., IBM Corp., Research Triangle Park, NC, USA

Volume

1

fYear

1995

fDate

23-26 Oct 1995

Firstpage

69

Abstract

IBM Mwave^TM has developed a radically new approach for real-time video and graphics processing. A scalable array of processing elements (PEs) is configured as a “folded array” for effective execution of matrix and transpose operations. The single chip Mwave Folded Array Signal Transform processor (MFAST) is a scalable DSP that provides 10+ billion 16-bit operations-per-second@50 MHz, sustainable during algorithm execution. This paper describes key M.F.A.S.T. elements and a bounded 18-22 cycle 8×8-pixel 2-D discrete cosine transform (DCT) program, verified on VHDL and functional simulator models

Keywords

digital signal processing chips; discrete cosine transforms; hardware description languages; parallel architectures; real-time systems; video signal processing; 16 bit/s; 2D DCT program; 50 MHz; IBM Mwave; MFAST; Mwave Folded Array Signal Transform processor; VHDL; algorithm execution; discrete cosine transform; folded array; functional simulator models; graphics processing; matrix operations; real-time video processing; scalable DSP; scalable array of processing elements; single chip highly parallel image processing architecture; transpose operations; Communication system control; Data buses; Decoding; Delay; Discrete cosine transforms; Encoding; Image processing; Joining processes; Topology; Two dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1995. Proceedings., International Conference on

Conference_Location

Washington, DC

Print_ISBN

0-8186-7310-9

Type

conf

DOI

10.1109/ICIP.1995.529041

Filename

529041