DocumentCode :
1945453
Title :
Future Bipolar Device Structures
Author :
Goto, H.
Author_Institution :
Bipolar Process Engineering Department, Fujitsu Limited, 1015, Kamikodanaka, Nakahara, Kawasaki 211, Japan
fYear :
1988
fDate :
13-16 Sept. 1988
Abstract :
Recently developed bipolar device structures including their problems and future trends are reviewed. Polysilicon emitter-base self-aligned structures and trench isolation techniques are becoming key elements for high performance bipolaw ECL device structures, by which parasitic capacitances and resistances have been reduced drastically. In order to get further improved performance, smaller parasitic capacitances associated with the pull-up resistor as well as high cutoff frequency are required. Wafer-direct-bonded SOI structures are the promising candidate, while the base resistance and the cutoff frequency should be optimized moderately. The most serious problem is the power dissipation of ECL-type circuits. Smaller logic swings and low temperature operation should be also considered.
Keywords :
BiCMOS integrated circuits; Cutoff frequency; Electrodes; Logic devices; Parasitic capacitance; Power dissipation; Resistors; Stacking; Transistors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location :
Montpellier, France
Print_ISBN :
2868830994
Type :
conf
Filename :
5436947
Link To Document :
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