DocumentCode
1945536
Title
An acceleration of a graph cut segmentation with FPGA
Author
Kobori, Daichi ; Maruyama, Tsutomu
Author_Institution
Syst. & Inf. Eng., Univ. of Tsukuba, Tsukuba, Japan
fYear
2012
fDate
29-31 Aug. 2012
Firstpage
407
Lastpage
413
Abstract
Image segmentation is one of the most important steps in image processing. The graph cut is an effective method for the image segmentation. For calculating the graph cut, the max-flow algorithm is widely used, but it requires long computation time. To execute the graph cut in real-time, the acceleration of max-flow algorithm with hardware is necessary. In this paper, we propose an implementation of a max-flow problem for the image segmentation on FPGA. In this system, the push-relabel method and the gap relabeling are used in order to achieve high performance on FPGA. The performance is 20-30 fps for standard benchmark images.
Keywords
field programmable gate arrays; graph theory; image segmentation; FPGA; gap relabeling; graph cut segmentation acceleration; image processing; image segmentation; max-flow algorithm; push-relabel method; standard benchmark images; Abstracts; Acceleration; Barium; Field programmable gate arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location
Oslo
Print_ISBN
978-1-4673-2257-7
Electronic_ISBN
978-1-4673-2255-3
Type
conf
DOI
10.1109/FPL.2012.6339137
Filename
6339137
Link To Document