An FPGA acceleration of a level set segmentation method

Image segmentation is one of the most important tasks in the image processing. The level set method is a powerful algorithm for the segmentation. In the level set method, a three-dimensional auxiliary function is used for detecting objects of various shapes. Its computational complexity is, however, very high, and many techniques have been proposed to reduce the computational complexity. In this paper, we describe a new algorithm for the level set method and its FPGA implementation. This algorithm is (1) designed so as to allow deep pipelining on hardware systems, and (2) able to detect all objects in the image, which is difficult for previous level set algorithms. We have implemented the algorithm on Xilinx XC4VLX160, and its performance is about 700 fps for 640 × 480 pixel images.