• DocumentCode
    1945621
  • Title

    Analytical computation of packet latency in a 2D-mesh NoC

  • Author

    Foroutan, Sahar ; Thonnart, Yvain ; Hersemeule, Richard ; Jerraya, Ahmed

  • Author_Institution
    STMicroelectron., Geneva, Switzerland
  • fYear
    2009
  • fDate
    June 28 2009-July 1 2009
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In order to avoid time-consuming iterations in the design flow of system-on-chip communication, it is required to make early decisions based on the performance estimations of the system. To fulfill such requirements, analytical techniques are fast and reliable alternatives for long and non-exhaustive traditional simulation-based methods. This paper presents a case-study of using an analytical method, based on Markov chain stochastic processes, for latency evaluation of a Network-on-Chip arranged in a two dimensional Mesh topology, with an x-first routing algorithm and an uniform traffic pattern. Results obtained by the analytical method are compared with the results of a SystemC simulation platform.
  • Keywords
    Markov processes; delays; network routing; network topology; network-on-chip; 2D-mesh NoC; Markov chain; SystemC simulation; analytical computation; end-to-end communication; link-acquisition-delay; link-transfer-delay; network-on-chip; packet latency; stochastic processes; two dimensional mesh topology; uniform traffic pattern; x-first routing algorithm; Algorithm design and analysis; Analytical models; Delay; Network topology; Network-on-a-chip; Pattern analysis; Routing; Stochastic processes; System-on-a-chip; Telecommunication network reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on
  • Conference_Location
    Toulouse
  • Print_ISBN
    978-1-4244-4573-8
  • Electronic_ISBN
    978-1-4244-4574-5
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2009.5290419
  • Filename
    5290419