Automatic verification methodology based on structural test patterns

Author

Hobeika, Christelle ; Thibeault, Claude ; Boland, Jean François

Author_Institution

Electr. Eng. Dept., Ecole de Technol. Super., Montreal, QC, Canada

fYear

2009

fDate

June 28 2009-July 1 2009

Firstpage

1

Lastpage

4

Abstract

Functional verification is a major bottleneck in today´s design flow. Current technologies are not meeting the challenges imposed by design complexity. In this paper, we propose a new simulation-based verification methodology based on the use of automatically generated structural test patterns in the RTL simulation. The presented approach generally improves the simulation-based verification´s quality, keeping the integration, the applicability and the automation aspects in close proximity.

Keywords

automatic test pattern generation; circuit CAD; circuit complexity; circuit simulation; formal verification; integrated circuit design; integrated circuit testing; RTL simulation; automatic verification methodology; design complexity; design flow; functional verification; simulation-based verification; structural test pattern; Acoustic testing; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Design for testability; Observability; Registers; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on

Conference_Location

Toulouse

Print_ISBN

978-1-4244-4573-8

Electronic_ISBN

978-1-4244-4574-5

Type

conf

DOI

10.1109/NEWCAS.2009.5290420

Filename

5290420