DocumentCode
1945826
Title
A low complexity VLSI architecture for MIMO sphere decoding algorithm
Author
Shariat-Yazdi, Ramin ; Kwas, Tad
Author_Institution
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
fYear
2009
fDate
June 28 2009-July 1 2009
Firstpage
1
Lastpage
4
Abstract
This paper presents a low complexity VLSI architecture for depth-first sphere decoding algorithm. A modified depth first sphere decoding algorithm that requires less hardware resources and provides higher throughput has been introduced. In order to implement the proposed algorithm, we introduce a new enumeration methodology that can be used for M-QAM based modulation schemes. The effectiveness of the proposed architecture has been demonstrated for a 4times4 64-QAM MIMO system.
Keywords
MIMO communication; VLSI; decoding; 64-QAM MIMO system; M-QAM based modulation schemes; MIMO sphere decoding algorithm; low complexity VLSI architecture; modified depth first sphere decoding algorithm; multiple-input multiple-output communication; Additive noise; CMOS technology; Detectors; Gaussian noise; MIMO; Maximum likelihood decoding; Maximum likelihood detection; Sorting; Transmitters; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on
Conference_Location
Toulouse
Print_ISBN
978-1-4244-4573-8
Electronic_ISBN
978-1-4244-4574-5
Type
conf
DOI
10.1109/NEWCAS.2009.5290429
Filename
5290429
Link To Document