DocumentCode :
1945835
Title :
An energy-efficient hardware accelerator for Robust Header Compression in LTE-Advanced terminals
Author :
Traboulsi, Shadi ; Zhang, Wenlong ; Szczesny, Daivd ; Showk, Anas ; Bilgic, Attila
Author_Institution :
Inst. for Integrated Syst., Ruhr-Univ. Bochum, Bochum, Germany
fYear :
2012
fDate :
29-31 Aug. 2012
Firstpage :
691
Lastpage :
694
Abstract :
In this paper we present an efficient hardware architecture for accelerating the Robust Header Compression version 2 (ROHCv2) algorithm in Long Term Evolution (LTE) mobile devices. The proposed hardware accelerator and its software variant are evaluated on an FPGA-based SoC. Our results show that the advised hardware architecture provides processing speeds (2.9 Gbit/s) beyond LTE-Advanced. Moreover, it increases the compression speed by 14-fold and reduces power consumption by 37%, compared to the software solution. The hardware is further optimized to handle multiple packet flows by employing a shared context buffer, thereby lowering the energy consumption of the ROHC hardware by 21% and ceasing degradation in compression rate.
Keywords :
Long Term Evolution; data compression; field programmable gate arrays; system-on-chip; FPGA-based SoC; LTE-Advanced; LTE-advanced terminals; Long Term Evolution mobile devices; ROHCv2 algorithm; bit rate 2.9 Gbit/s; energy consumption; energy-efficient hardware accelerator; multiple packet flows; power consumption; robust header compression version 2 algorithm; shared context buffer; software variant; Buffer storage; Computer architecture; Context; Encoding; Hardware; IP networks; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location :
Oslo
Print_ISBN :
978-1-4673-2257-7
Electronic_ISBN :
978-1-4673-2255-3
Type :
conf
DOI :
10.1109/FPL.2012.6339154
Filename :
6339154
Link To Document :
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