Title :
A digitally tuned Voltage Controlled Delay Element for 1-10GHz DLL-based frequency synthesis
Author :
De Peslouan, Pierre Olivier Lucas ; Majek, C. ; Taris, T. ; Deval, Y. ; Belot, D. ; Begueret, J.B.
Author_Institution :
IMS Lab., Univ. of Bordeaux, Talence, France
fDate :
June 28 2009-July 1 2009
Abstract :
This paper presents an original topology for Voltage Controlled Delay Element used in a DLL-based oscillator. This cell works from 1 to 10 GHz achieving the phase noise performances required for the targeted wireless standards. The current consumption is lower than 9 mA under 1 V supply voltage. Thanks to the new topology a delay bank control scheme is feasible, paving the way to digitally controlled DLL.
Keywords :
delay lock loops; oscillators; DLL-based frequency synthesis; DLL-based oscillator; delay locked loop; digitally tuned voltage controlled delay elements; frequency 1 GHz to 10 GHz; phase noise; wireless standards; Counting circuits; Delay; Digital control; Frequency synthesizers; Phase noise; Signal synthesis; Switches; Topology; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on
Conference_Location :
Toulouse
Print_ISBN :
978-1-4244-4573-8
Electronic_ISBN :
978-1-4244-4574-5
DOI :
10.1109/NEWCAS.2009.5290432
