DocumentCode
1945933
Title
Parallel PLA fault simulation based on Boolean vector operations
Author
Chiprout, E. ; Rajski, J. ; Robinson, M.
Author_Institution
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
fYear
1988
fDate
7-10 Nov. 1988
Firstpage
194
Lastpage
197
Abstract
An efficient PLA crosspoint fault simulation algorithm is presented. Parallel Boolean vector operations on a bitwise representation of PLA faults replace set operations, leading to increasing efficiency as the PLA size grows. Experimental results demonstrate execution times averaging over 100% faster than PLATYPUS and almost two and a half orders of magnitude faster than the CHIEFS fault simulator.<>
Keywords
Boolean algebra; circuit analysis computing; digital simulation; fault location; logic arrays; parallel algorithms; vectors; Boolean vector operations; CHIEFS; PLA crosspoint fault simulation algorithm; PLA size; PLATYPUS; bitwise representation; efficiency; execution times; parallel algorithm; set operations; Automatic test pattern generation; Compaction; Costs; Councils; Fabrication; Fault detection; Mirrors; Programmable logic arrays; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-0869-2
Type
conf
DOI
10.1109/ICCAD.1988.122492
Filename
122492
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