DocumentCode
1946048
Title
A parallel architecture for video compression
Author
Bhattacharjee, S. ; Das, S. ; Saha, D. ; Chowdhury, D. Roy ; Chaudhuri, P. Pal
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear
1997
fDate
4-7 Jan 1997
Firstpage
247
Lastpage
252
Abstract
This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames per second with frame size of 352×272 pixels
Keywords
data compression; parallel architectures; pipeline processing; video coding; 272 pixel; 352 pixel; 95744 pixel; decompression; frame size; on-line compression/decompression; parallel architecture; pipelined architecture; throughput; video compression; video data files; Data compression; Decoding; Hardware; Image sequences; Layout; Parallel architectures; Throughput; Transform coding; Very large scale integration; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
0-8186-7755-4
Type
conf
DOI
10.1109/ICVD.1997.568084
Filename
568084
Link To Document