DocumentCode
1946071
Title
A Sub-Micron CMOS Process Employing Trench Isolation
Author
Roberts, M C ; Bolbot, P H ; Foster, D J
Author_Institution
Plessey Research Caswell Ltd., Caswell, Towcester, GB-Northants NN12 8EQ, Great-Britain
fYear
1988
fDate
13-16 Sept. 1988
Abstract
A high density trench isolated CMOS process has been developed. Circuit designs have been initially fabricated at 1¿m dimensions. Excellent device performance is demonstrated at channel lengths of O.7¿m and channel widths of O.2¿m showing the potential for fabricating circuits with 0.7¿m and 0.5¿m design rules.
Keywords
CMOS process; CMOS technology; Circuit synthesis; Electric breakdown; Etching; Implants; Isolation technology; MOS devices; Temperature; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location
Montpellier, France
Print_ISBN
2868830994
Type
conf
Filename
5436979
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