Efficient high-speed CIC decimation filter

Author

Yong Khoo, Kei ; Yu, Zhan ; Wilson, A.N.

Author_Institution

Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA

fYear

1998

fDate

13-16 Sep 1998

Firstpage

251

Lastpage

254

Abstract

This paper presents an efficient architecture for the first carry-save integrator stage in a high-speed cascaded integrator-comb (CIC) decimation filter based on exploiting the carry propagation properties in a carry-save accumulator. The architecture can reduce the number of registers (by 6.3% to 13.5% in our examples) and replace a large number of full-adders by half-adders (18% to 42% in our examples), thus saving area and power. Significant savings are achieved when the decimation rate is high and the number of integrator stages is small

Keywords

application specific integrated circuits; digital arithmetic; digital filters; high-speed integrated circuits; integrating circuits; carry propagation properties; carry-save accumulator; carry-save arithmetic; carry-save integrator stage; cascaded integrator-comb; full-adders; half-adders; high-speed CIC decimation filter; registers reduction; Clocks; Digital filters; Filtering; Finite impulse response filter; High speed integrated circuits; Laboratories; Registers; Sampling methods; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.722984

Filename

722984