Combining data and computation transformations for fine-grain reconfigurable architectures

This paper presents a project that aims to develop techniques for optimal code generation for High Performance Computing using reconfigurable hardware. Some problems faced are related to memory access, since the latency for data reading and writing became a bottleneck for HPC applications. The project is a branch of a system for hardware acceleration in HPC applications currently being developed at University of Sao Paulo, Brazil. This system intends to facilitate the development of HPC architectures for efficiently exploit of parallelism.