Title :
A low power Class D audio amplifier with discrete time loop filter compensation
Author :
Forzley, Tony ; Mason, Ralph
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, ON, Canada
fDate :
June 28 2009-July 1 2009
Abstract :
This brief describes a new Class D amplifier topology with digital input and a digital compensation loop filter to improve linearity. The core of the system is a high resolution hybrid multi-bit SigmaDelta-Pulse Width Modulation (PWM) modulator. The modulator does not require dynamic element matching nor signal processing to correct for distortion arising from the discrete PWM process. A system prototype based on a FPGA and commercial 16b analog to digital converter (ADC) validate the system design before implementation in 0.13 mum CMOS. Measurement results at 1 kHz yield a Total Harmonic Distortion (THD) better than 0.03% and greater than 30 dB of noise rejection and linearity enhancement. The system is inherently scalable to deep submicron processes due to its predominately digital architecture.
Keywords :
CMOS digital integrated circuits; audio-frequency amplifiers; digital filters; field programmable gate arrays; harmonic distortion; low-power electronics; pulse width modulation; sigma-delta modulation; CMOS; FPGA; analog to digital converter; digital compensation loop filter; discrete PWM; discrete time loop filter compensation; frequency 1 kHz; high resolution hybrid multi-bit SigmaDelta-pulse width modulation; low power Class D audio amplifier; modulator; size 0.13 mum; total harmonic distortion; Analog-digital conversion; Digital filters; Distortion; Field programmable gate arrays; Linearity; Prototypes; Pulse width modulation; Signal processing; Signal resolution; Topology;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on
Conference_Location :
Toulouse
Print_ISBN :
978-1-4244-4573-8
Electronic_ISBN :
978-1-4244-4574-5
DOI :
10.1109/NEWCAS.2009.5290462
