Area minimization for library-free synthesis

Current standard cell libraries are not well equipped to take full advantage of advances in deep submicron technology by implementing functions as complex gates. In a technology process capable of supporting five serial MOS devices, 425,803 unique complex gates may be created-clearly much higher than what is currently available in today´s cell libraries. A richer cell library allows the technology mapper more freedom to better select matches to reduce area, delay and power consumption. This paper proposes a novel algorithm for mapping an input netlist to a library of virtual cells to select an architecture which minimizes the design area. Simulation results show an average of 64.93% reduction in transistor count, 51.72% reduction in circuit area at the cost of 5.72% increase in delay by applying this algorithm to standard benchmark circuits compared to results obtained from Synopsys Design Compiler with high map effort for delay minimization.