Time domain current waveform simulation of CMOS circuits

Author

An-Chang Deng ; Yan-Chyuan Shiau ; Loh, K.-H.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1988

fDate

7-10 Nov. 1988

Firstpage

208

Lastpage

211

Abstract

A time-domain current waveform simulator for the power buses of CMOS circuits is presented. The use of the simulated waveform helps solve VLSI reliability problems due to electromigration and excessive voltage drops in the power bus. Based on the event-driven technique and the precharacterized switch-level delay model, the simulator can handle circuits as large as 10/sup 3/ approximately 10/sup 4/ transistors in 10 approximately 100 CPU seconds on the Sun-3 workstation. The simulated waveform in worst cases may deviate only 20% from those computed by SPICE.<>

Keywords

CMOS integrated circuits; VLSI; circuit analysis computing; delays; digital simulation; electric current; electromigration; reliability; 10 to 100 s; CMOS circuits; Sun-3 workstation; VLSI reliability; electromigration; event-driven technique; excessive voltage drops; power buses; precharacterized switch-level delay model; time-domain current waveform simulator; Circuit simulation; Computational modeling; Delay; Discrete event simulation; Electromigration; Semiconductor device modeling; Switching circuits; Time domain analysis; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-0869-2

Type

conf

DOI

10.1109/ICCAD.1988.122495

Filename

122495