Architecture and FPGA implementation of a 10.7 Gbit/s OTN Regenerator for optical communication systems

As the newest FPGA technologies provide high operating frequencies, in conjunction with serializer/deserializer hardwired modules enabling the operation of high data rate protocols, these devices are being increasingly used in high-speed telecommunication systems. This paper presents the architecture and development of an OTN OTU2 Regenerator that operates in 10.7 Gbit/s, fully implemented in a programmable logic device. 3-R regeneration, OTU overhead processing and error correction are realized in the OTU2 received frames by the digital logic developed. The aim of this work is to present the implementation feasibility of an OTN processor in FPGAs with applications in optical communication systems. A prototype was implemented in a Xilinx Virtex-6 device. Synthesis and timing results are also reported.