Title :
Novel wafer-level CSP for stacked MEMS / IC dies with hermetic sealing
Author :
Sugizaki, Yoshiaki ; Nakao, Mitsuhiro ; Higuchi, Kazuhito ; Miyagi, Takeshi ; Obata, Susumu ; Inoue, Michinobu ; Endo, Mitsuyoshi ; Shimooka, Yoshiaki ; Kojima, Akihiro ; Mori, Ikuo ; Shibata, Hideki
Author_Institution :
Center for Semicond. R&D, Toshiba Corp., Kawasaki
Abstract :
Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires were used for not only connecting stacked dies with one another but also for connecting from each die to CSP terminals. The WL-CSP is also applicable to microelecrromechanical system (MEMS) that requires hermetic sealing. Thin-film encapsulation for MEMS was formed by conventional back end of line (BEOL) process. Followed by die stacking and gold wire forming, chemical vapor deposition (CVD) was applied to make hermetic sealing. The WL-CSP does not require photolithography process on topography wafer. It promises a cost-effective solution for MEMS/IC dies coupled device.
Keywords :
chemical vapour deposition; encapsulation; hermetic seals; micromechanical devices; thin films; wafer level packaging; MEMS-IC dies coupled device; back end of line; chemical vapor deposition; gold bonding wires; hermetic sealing; microelecrromechanical system; stacked MEMS-IC dies; thin-film encapsulation; topography wafer; wafer-level chip scale package; Chip scale packaging; Gold; Joining processes; Micromechanical devices; Stacking; Surfaces; Transistors; Wafer bonding; Wafer scale integration; Wires;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4550068
