An all-digital PLL for satellite based navigation in 90 nm CMOS

New wireless communication devices comprehend more and more functionality. The number of existing and supported communication and RF standards is increasing. On the other hand the integration of analog and mixed-signal RF circuitry becomes more complex, as advanced deep-submicrometer CMOS processes usually do not offer any analog extension. On the system level the use of reconfigurable multimode architectures becomes more and more important. On the circuit level more digital intensive approaches become possible and are implemented instead of classical pure analog or mixed-signal topologies. In this work an all-digital PLL for a multimode shared RF low-power receiver for satellite based navigation is presented. It has been designed as a fully integrated single-chip PLL in a 90 nm CMOS technology to be compatible with digital deep-submicrometer processes. Target application of the proposed system is the co-integration with other RF circuitry and digital baseband processors for mobile communication systems. As mobile applications are the main target for the PLL great attention has been attached to saving power and area. Therefore, the presented PLL works on a 1 V supply voltage.