DocumentCode
1946960
Title
Half-Micrometer N-MOS Technology for Gigabit Logic
Author
Guegan, G. ; Lerme, M. ; Gautier, J. ; Guerin, M. ; Tedesco, Salvatore ; Dal´zotto, B. ; Reimbold, S. Tedescog
Author_Institution
Division LETI, IRDI, DMEL/S. MSC, CENG, 85X, F-38041 Grenoble Cedex, France
fYear
1988
fDate
13-16 Sept. 1988
Abstract
In order to point out the performances of NMOS technology, a fully-scaled 0.5 ¿m enhancement/depletion NMOS process was integrated and compared with other technologies, using the same test circuit : a three bit feed-back adder. The average experimental maximum frequency of operation is 1 GHz which is better than results obtained on GaAs LPBFL for about the same power consumption and number of logic layers (10) but lightly shorter gate length.
Keywords
Adders; Circuit testing; Gallium arsenide; Integrated circuit technology; Lithography; Logic; MOS devices; Performance evaluation; Propagation delay; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location
Montpellier, France
Print_ISBN
2868830994
Type
conf
Filename
5437025
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