Title :
Methodology for process portable hard IP block creation using cell based array architecture
Author :
Gopisetty, Runip ; Hsu, Kirk ; Chakankar, Abhijit
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
A methodology for hard IP creation and an automated “process tuned” migration of this IP block is presented. The flow for hard IP creation using the CBA Block Export Flow is presented. Salient features of this include automated IP block timing model creation and physical view creation allowing easy encapsulation of the IP core into a chip level environment. Following this, a flow for automatically porting this IP core so that it is optimally implemented in the target process using CBA Block Transport is presented
Keywords :
application specific integrated circuits; cellular arrays; circuit CAD; high level synthesis; integrated circuit design; ASIC design; CAD; CBA block export flow; CBA block transport; IP block timing model creation; cell based array architecture; chip level environment; design methodology; physical view creation; process portable hard IP block creation; Design optimization; Encapsulation; Fabrics; Field programmable gate arrays; Kirk field collapse effect; Logic arrays; Power system modeling; Programmable logic arrays; Time to market; Timing;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.722992
