Title :
The bus interface and paging units of the i860 microprocessor
Author :
Rhodehamel, Michael W.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The i860 microprocessor is a one-million-transistor, high-performance, 64-b RISC (reduced-instruction-set-computer)-based microprocessor. The performance of the i860 at 40 MHz is 83000 Dhrystones, 24 double-precision MWhetstones, and 10 double-precision MFLOPS on the Linpack benchmark. To support this rate of integer and floating-point execution a bus interface unit and paging unit were designed to provide the needed bus bandwidth. The bus and paging units, in conjunction with the internal data and instruction caches, can provide a 960-Mbyte internal instruction and data bus bandwidth, and a 160-Mbyte external bus bandwidth
Keywords :
microprocessor chips; reduced instruction set computing; virtual storage; 160 Mbyte/s; 960 Mbyte/s; RISC; bus bandwidth; bus interface unit; floating-point execution; i860 microprocessor; instruction caches; paging units; performance; Bandwidth; Clocks; Delay; Hardware; Microprocessors; Pins; Pipeline processing; Random access memory;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63392
