Title :
Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost
Author :
Kuo, Tzu-Ying ; Chang, Shu-Ming ; Shih, Ying-Ching ; Chiang, Chia-Wen ; Hsu, Chao-Kai ; Lee, Ching Kuan ; Lin, Chun-Te ; Chen, Yu-Hua ; Lo, Wei-Chung
Author_Institution :
Packaging Technol. Div., EOL/ITRI, Hsinchu
Abstract :
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through Si via connections were formed by UV laser drilling technology. Laser drilling is a non-contact manufacture method and laser beam with high energy can be focused to a small spot (15 mum beam diameter) for material ablating and removing without mask used. Several processes are the keys to accomplish 3D stacking, such as wafer thinning process, through silicon via forming process, dielectric layer forming process, metallization process, and inter chips bonding process. By integration of the mentioned key processes, a 3D chip stacking structure with 10 layers was carried out. The thickness of chip was 100 mum. Daisy chain pattern was designed for the electrical measurement of 3D stacking structure. The testing results show that the resistance of multi- chip stacking structure is about 0.056 Omega/cm. Some reliability test, such as temperature cycling test and pressure cooker test were also done. These testing results verified this PCB processing compatible 3D chip stacking technology with low cost is a reliable structure for 3D SiP (System in Packaging) module application.
Keywords :
elemental semiconductors; integrated circuit bonding; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; laser beam machining; printed circuits; silicon; system-in-package; wafer level packaging; 3D system in packaging module application; PCB processing compatible structure; UV laser drilling technology; chip thickness; daisy chain pattern; dielectric layer forming process; inter chips bonding process; metallization process; pressure cooker test; printed circuit board; reliability tests; temperature cycling test; three dimensional chip stacking structure; through silicon via forming process; wafer thinning process; Circuit synthesis; Circuit testing; Costs; Drilling; Energy consumption; Laser beams; Packaging; Printed circuits; Silicon; Stacking;
Conference_Titel :
Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-2230-2
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2008.4550076