Combining circuit level changes with electrical optimization

A program, called EPOXY, which sizes a circuit´s transistors to satisfy performance and area constraints is discussed. If these cannot be met, the program considers small circuit changes in an effort to meet the constraints. Several CMOS examples demonstrate how EPOXY applies these heuristics to meet difficult timing constraints, power requirements, and cell width and height limitations. Compact layout and aspect-ratio requirements are handled by a virtual grid area model. From an implementation viewpoint, EPOXY´s underlying equation representation of circuit performance automatically provides critical path information and allows rapid modification of the circuit structure. When EPOXY was applied to a CMOS 16-bit adder, a speed improvement of 23% was achieved over transistor sizing alone while satisfying a height constraint. Similarly, the speed of a dynamic CMOS PLA was improved by 10% and that of an array of CMOS JK flip-flops by 23%.<>