Title :
An experimental investigation of EEPROM reliability issues using the progressional offset technique
Author :
Chester, A.J. ; Walton, A.J. ; Tuohy, P.
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
Abstract :
A set of novel EEPROM test structures have been designed and fabricated, in which gate/drain overlap is incremented in a number of well defined steps. These have been used to emulate EEPROM programming conditions, and measure endurance. The structures have enabled EEPROM endurance to be investigated as a function of drain doping species (As and P), for a spectrum of floating gate/drain overlaps
Keywords :
EPROM; MOS integrated circuits; PLD programming; circuit reliability; doping profiles; integrated circuit testing; EEPROM reliability; EEPROM test structures; Si:As; Si:P; drain doping species; endurance measurement; floating gate/drain overlaps; programming conditions emulation; progressional offset technique; Doping; EPROM; Electrons; Fabrication; MOSFETs; Microprocessors; Nonvolatile memory; Read only memory; Testing; Tunneling;
Conference_Titel :
Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1757-2
DOI :
10.1109/ICMTS.1994.303472
