Title :
Optimizing test hardware for at-speed testing of datapaths in an integrated circuit
Author :
Bhattacharya, Debashis ; Freeman, Smith ; Lin, Bill
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
In this paper, we introduce a new representation method for datapath tests-called test template representation-and also introduce a new analysis technique to minimize the test logic overhead, through careful processing of the test templates. The resultant test structures represent the next systematic step beyond the multiplexer bypass method commonly found in commercial test tools
Keywords :
VLSI; design for testability; integrated circuit design; integrated circuit testing; logic design; logic testing; analysis technique; at-speed testing; datapaths; integrated circuit; representation method; test hardware optimisation; test logic overhead minimisation; test template representation; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Hardware; Integrated circuit testing; Logic testing; Manuals; Multiplexing; System testing;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568092
