DocumentCode
1947201
Title
Assessment of electro-static discharge robustness based on the monitoring of lattice temperature of silicon
Author
Yoo, Kwang D. ; Lim, Gwang H. ; Jin, Joo H. ; Choi, Kyu H.
Author_Institution
Semicond. R&D, Samsung Electron., Kyunggi, South Korea
fYear
1994
fDate
22-25 Mar 1994
Firstpage
208
Lastpage
213
Abstract
In this paper, we demonstrate that it is possible to develop an optimum ESD protection device by comparing the relative ESD robustness of each device, based on the monitoring of the peak temperature correlated with the peak power density. The methodology, supported by measurement data, could give an extra degree of freedom to IC designers confronted with the troublesome ESD phenomenon
Keywords
MOS integrated circuits; electrostatic discharge; integrated circuit technology; integrated circuit testing; protection; silicon; temperature distribution; IC design; Si; electrostatic discharge robustness; lattice temperature; optimum ESD protection device; peak power density; peak temperature; Biological system modeling; Circuit simulation; Electrostatic discharge; Lattices; Monitoring; Protection; Robustness; Silicon; Temperature measurement; Temperature sensors;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1757-2
Type
conf
DOI
10.1109/ICMTS.1994.303474
Filename
303474
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