A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization

Author

Balan, Vishnu ; Caroselli, Joe ; Chern, J.-G. ; Desai, Chintan ; Liu, Cathy

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

31

Lastpage

34

Abstract

In this paper, a serial link design that is capable of 4.8-6.4 Gbps binary NRZ signaling across 40" of FR4 copper back plane and two connectors is described. The transmitter features a programmable feed forward (FF) equalizer and the receiver uses adaptive decision feedback equalization (DFE) to compensate for the losses in the channel. The transceiver core is built in a 0.13 μm standard CMOS technology to be integrated into ASIC chips that require serial links.

Keywords

CMOS integrated circuits; equalisers; telecommunication links; 0.13 micron; 4.8 to 6.4 Gbit/s; 40 inch; ASIC chips; CMOS; Cu; DFE; adaptive decision feedback equalization; backplane serial link; binary NRZ signaling; channel loss compensation; programmable feed forward equalizer; receiver; transceiver core; transmitter; CMOS technology; Connectors; Copper; Decision feedback equalizers; Feeds; Optical signal processing; Propagation losses; Signal design; Transceivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358726

Filename

1358726