A negative resistance compensated switching current sampled-and-hold circuit

Author

Shen, Ding-Lan ; Lee, Wei-Tseh

Author_Institution

Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan

fYear

2009

fDate

June 28 2009-July 1 2009

Firstpage

1

Lastpage

4

Abstract

A switching current sample-and-hold circuit utilizing negative resistance compensation to enhance the output impedance of the current cell is presented. This paper demonstrates the principle of negative-resistance applications in switching current cells. The proposed switching current sample-and-hold circuit achieves 44.6 dB SNDR and 58.5 dB SFDR with a 4 MHz input of 40 MS/s sampling frequency at the 1.2 V supply voltage of CMOS 0.35-mum technology.

Keywords

CMOS analogue integrated circuits; electrical resistivity; low-power electronics; sample and hold circuits; switching circuits; CMOS technology; current cell; frequency 4 MHz; low-voltage circuit design; negative resistance compensation; output impedance; size 0.35 mum; switching current sample-and-hold circuit; voltage 1.2 V; CMOS technology; Circuit synthesis; Clocks; Immune system; Impedance; Integrated circuit technology; Low voltage; Sampling methods; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on

Conference_Location

Toulouse

Print_ISBN

978-1-4244-4573-8

Electronic_ISBN

978-1-4244-4574-5

Type

conf

DOI

10.1109/NEWCAS.2009.5290493

Filename

5290493