Title :
Automatic process monitor generation
Author_Institution :
Information Sci. Inst., Marina del Rey, CA, USA
Abstract :
In this paper we introduce a system for automatically generating layout, test procedure and report generation files for parametric and functional process monitor test structures. This system has been in production use at the MOSIS Service for several years with a variety of CMOS technologies. We will show how these files are generated with a mixed set of specifications, then integrated into a test system software environment and report generator
Keywords :
CMOS integrated circuits; automatic testing; circuit layout CAD; computerised monitoring; integrated circuit testing; CMOS technologies; MOSIS Service; automatic process monitor generation; layout generation; process monitor test structures; report generation files; test procedure; test system software environment; Automatic testing; CMOS technology; Computerized monitoring; Condition monitoring; Electrical resistance measurement; Fabrication; Inspection; Packaging; Software testing; System testing;
Conference_Titel :
Microelectronic Test Structures, 1994. ICMTS 1994. Proceedings of the 1994 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-1757-2
DOI :
10.1109/ICMTS.1994.303481
