Validation of warpage limit for successful component surface mount (SMT)

Coplanarity and flatness of electronic components have been identified as some of the key parameters for a good component surface mount (SMT) along with the associated reflow-profile and moisture condition. Currently, the coplanarity of components is specified at room temperature in industry standards such as JEP95. The current room temperature specifications often fail to ensure proper SMT process as they do not account for temperature dependent behavior of components during reflow process. There is a need to establish a method to better reflect the component behavior. Recently, there was attempt [1] to shift away from room temperature measurement towards a measurement at reflow temperatures. However, before such methods can be implemented, one must determine the limits of solder joint formation with respect to the warpage of components. In order to perform successful SMT assembly, there is need to understand and quantify the boundaries of the geometric relationship among the component, solder paste and board. In order to explore these boundaries, two experiments were conducted; "single solder joint forming experiment", and "bent substrate SMT experiment". The results of these two experiments can then supplement the limited data available in the literature to provide the effect of the coplanarity budget for successful joint formation. A comparison between results shows very consistent trends despite the use of very distinct measurement methods. This work then creates a foundation for developing more robust package requirements to ensure high quality SMT connections.